1. Field of the Invention
The present invention relates generally to a semiconductor device having a multilayered interconnection structure, and more particularly, to a method of fabricating a semiconductor device having a dual damascene structure.
2. Description of Prior Art
It has been important to make interconnections fine and multilayered as semiconductor integrated circuits have been increased in integration density. Dual damascene structures for simultaneously forming trench interconnections and via holes have been paid attention to because it is possible to reduce cost and increase throughput by reducing the number of steps, and it is possible to lower resistance and lengthen the life of electromigration by using Cu interconnections.
A method of forming a conventional dual damascene structure will be described with reference to FIGS. 2A to 2D.
As shown in FIG. 2A, a lower trench interconnection layer 31 is formed using copper (Cu), and a protective film 32, an interlayer insulation film 33, an etch stopper film 34, and an interlayer insulation film 35 are deposited thereon as a first step. The Cu interconnection is easily oxidized when it reaches a high temperature of not less than 150xc2x0 C. in an atmosphere of oxygen or vapor, so that interconnection resistance is raised. Further, Cu in the interconnection is ionized and is diffused into a silicon dioxide film. Consequently, it is impossible to directly form the silicon dioxide film on the Cu interconnection by plasma CVD (Chemical Vapor Deposition) because the Cu interconnection is oxidized and diffused.
Therefore, after the lower trench interconnection layer 31 is formed, the protective film 32 composed of a silicon nitride film is then provided on the interconnection. Further, the depth of a trench corresponds to the thickness of the interconnection. In order to prevent the interconnection resistance from varying, a trench having a uniform depth must be formed in the interlayer insulation film 35. In forming the interlayer insulation film 35, therefore, an etch stopper film 34 composed of a silicon nitride film having a high etching selection ratio to the silicon dioxide film is formed.
After the interlayer insulation films 33 and 35 are formed, as described above, a resist pattern 36 is formed by a normal exposure method, to provide a via hole 37 by anisotropic etching, as a second step, as shown in FIG. 2B. After the step, a resist pattern 38 is formed by a normal exposure method, to provide an interconnection portion with an opening 39 by anisotropic etching, as a third step, as shown in FIG. 2C.
Thereafter, a dual damascene interconnection structure is formed in the step of embedding a metal 40 such as copper, tungsten, or aluminum, as a fourth step, as shown in FIG. 2D.
On the other hand, capacitance between interconnections is increased by increasing the density of the interconnection, thereby preventing the speed of the semiconductor integrated circuit from being increased. As a method for solving the problem, an interlayer insulation film having a low dielectric constant is used.
Examples of the interlayer insulation film having a low dielectric constant which is applied to the dual damascene structure include a fluorine-added silicon oxide film, an organic SOG (Spin on Glass) film, and an organic polymer film.
SOG is a generic term of a film mainly composed of a solution obtained by dissolving a silicon compound in an organic solvent and silicon dioxide formed from the solution. The organic SOG film has an organic component contained in a silicon compound, as expressed by a general formula (1):
[RxSiOy]nxe2x80x83xe2x80x83(1) 
(n, x, y: an integer, R: an alkyl group or an aryl group).
The above-mentioned organic SOG film is superior in low dielectric constant, embedding properties, and cost. However, the organic SOG film on a sidewall of the via hole is brought into a void state in the second, third, and fourth steps, thereby making it impossible to obtain good electrical properties.
As described above, a silicon nitride film having a high dielectric constant is generally used for the protective film 32 and the etch stopper film 34 in the dual damascene structure. Even if a material having a low dielectric constant is used for the interlayer insulation film, therefore, the total capacitance between interconnections is increased. In order to avoid the increase, thinning of and an alternative to the silicon nitride film have been examined, which introduce a problem in terms of productivity and reliability.
By removing the protective film 32 at the bottom of the via hole after the second step, the lower interconnection layer is degraded at the time of removing resist in the third step, thereby raising resistance and degrading reliability.
The present invention has been made in view of such circumstances, and its object is to provide a method of fabricating a semiconductor device having a highly reliable multilayered interconnection.
A method of fabricating a semiconductor device according to the present invention is characterized by comprising the steps of forming a first insulation film on a first interconnection; forming a coating film on the first insulation film and forming a second insulation film which has been modified by implanting impurities into the coating film; forming a third insulation film serving as an etch stopper on the second insulation film; forming a coating film on the third insulation film and forming a fourth insulation film which has been modified by implanting impurities into the coating film; forming a resist pattern, and etching away the fourth insulation film, the third insulation film, and the second insulation film using the resist pattern, to form a via hole; etching away the fourth insulation film in order to form a recess serving as a trench interconnection portion using the resist pattern; etching away the third insulation film and the first insulation film which are exposed; and filling the recess with a conductive material, to form a conductive plug in the via hole and a second interconnection.
The present invention can be so constructed that the step of forming the second interconnection comprises the step of forming the second interconnection simultaneously with the via hole for electrically connecting the first interconnection and the second interconnection.
The second and fourth insulation films may use an organic polymer as the coating film, and may be modified by implanting impurities into the organic polymer by ion-implantation.
Organic SOG can be used as the organic polymer.
As described above, the present invention uses as an interlayer insulation film an insulation film having impurities contained in a coating film, for example, an organic SOG film which has been modified by ion-implanting impurities. The etching selection ratio of the insulation film which has been modified by containing the impurities in the coating film to the first and fourth insulation films respectively serving as a protective film and an etch stopper film is improved. For example, the etching selection ratio of the modified organic SOG film to the silicon nitride film is increased. Therefore, the first insulation film (the protective film) and the fourth insulation film (the etch stopper film) can be simultaneously removed after the via hole and the trench interconnection are provided.
As a result, according to the present invention, good via contact properties are obtained, and it is possible to reduce capacitance between interconnections by reducing the volume of the silicon nitride film as well as to obtain an interconnection having low resistance and high reliability by reducing damage to the lower interconnection layer.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.